1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, the present invention relates phase-change semiconductor memory devices and to methods of programming phase-change semiconductor memory devices.
A claim of priority is made to Korean Patent Application No. 10-2005-0028087, filed on Apr. 4, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
A phase-change random access memory (PRAM), also known as an Ovonic Unified Memory (OUM), includes a phase-change material such as a chalcogenide alloy which is responsive to heat so as to be stably transformed between crystalline and amorphous states. Such a PRAM is disclosed, for example, in U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase-change material of the PRAM exhibits a relatively low resistance in its crystalline state, and a relatively high resistance in its amorphous state. In conventional nomenclature, the low-resistance crystalline state is referred to a ‘set’ state and is designated logic “0”, while the high-resistance amorphous state is referred to as a ‘reset’ state and is designated logic “1”.
Generally, the phase-change material of a PRAM is reset to an amorphous state by heating the material in excess of its melting point temperature for a relatively short period of time. On the other hand, the phase-change material is set to a crystalline state by heating the material below its melting point temperature for a longer period of time.
The speed and stability of the phase-change characteristics of the phase-change material are critical to the performance characteristics of the PRAM. As suggested above, chalcogenide alloys have been found to have suitable phase-change characteristics, and in particular, a compound including germanium (Ge), antimony (Sb) and tellurium (Te) (e.g., Ge2Sb2Te5 or GST) exhibits a stable and high speed transformation between amorphous and crystalline states.
In addition to the differing resistive characteristics mentioned above, the phase-change material exhibits a relatively low reflexibility in its amorphous state, and a relatively high reflexibility in its crystalline state.
FIGS. 1A and 1B illustrate a memory cell 10 in a ‘set’ state and in a ‘reset’ state, respectively, and FIG. 2 is an equivalent circuit diagram of the memory cell 10 of FIGS. 1A and 1B. It should be noted that the connections illustrated in FIGS. 1A, 1B and 2 are presented as examples only, and that other configurations are possible. For example, the cell C (FIG. 2) may include a phase-change material connected to the bit line BL, and a diode (not shown) connected between the phase-change material and the word line WL.
In each of FIGS. 1A and 1B, the memory cell 10 includes a top electrode 12 formed on a phase-change material 14. In this example, the top electrode 12 is electrically connected to a bit line BL of a PRAM memory array (not shown). A conductive bottom electrode contact (BEC) 16 is formed between the phase-change material 14 and a conductive bottom electrode 18. An access transistor 20 is electrically connected between the bottom electrode 18 and a reference potential (e.g., ground). In this example, the gate of the access transistor 20 is electrically connected to a word line WL of the PRAM cell array (not shown).
In FIG. 1A, the phase-change material is illustrated as being in its crystalline state. As mentioned previously, this means that the memory cell 10 is in a low-resistance ‘set’ state or logic 0 state. In FIG. 1B, a portion of the phase-change material is illustrated as being amorphous. Again, this means that the memory cell 10 is in a high-resistance ‘reset’ state or logic 1 state.
The set and reset states of the memory cell 10 of FIGS. 1A and 1B are establish by controlling the magnitude and duration of current flow through the BEC 16. That is, as shown in FIG. 2, the cell C is activated (or accessed) by operation of the access transistor 20 which is responsive to a voltage of the word line WL. When activated, the cell C is programmed according to the voltage of the bit line BL. More specifically, the bit line BL voltage is controlled to establish a programming current ICELL which causes the BEC 16 to act as a resistive heater which selectively programs the phase-change material 14 in its ‘set’ and ‘reset’ states. This is explained in more detail below with reference to FIG. 3.
FIG. 3 illustrates an example of temperature pulse characteristics of phase-change material as the phase-change material is programmed in the ‘set’ and ‘reset’ states. In particular, reference number 35 denotes the temperature pulse of the phase-change material programmed to its ‘reset’ state, and reference number 36 denotes the temperature pulse of the phase-change material programmed to its ‘set’ state.
As shown in FIG. 3, when the phase-change material is programmed to its ‘reset’ state, the temperature of the material is increased above its melting temperature Tm (e.g., 610° C.) for a relatively short period of time, and then allowed to rapidly cool. In contrast, when the phase-change material is programmed to its ‘set’ state, the temperature of the material is increased to below its melting point Tm and above its crystallizing temperature Tx (e.g., 450° C.) for a longer period of time, and then allowed to cool. The temperature range between the melting temperature Tm and the crystallizing temperature Tx is referred to as the “set window”.
FIG. 4 is a diagram showing a set current pulse I_SET and a reset current pulse I_RESET that is applied to the phase-change memory cell in order to achieve the temperature pulse characteristics shown in FIG. 3. More particularly, the reset current pulse I_RESET is applied to achieve the temperature pulse 35 of FIG. 3, and the set current pulse I_SET is applied to achieve the temperature pulse 36 of FIG. 3. As one would expect, a larger current pulse of shorter duration is applied to place the phase-change material in its amorphous state than in its crystallize state.
As the operational voltage level of portable devices continues to decrease, it has become increasingly difficult to generate sufficient PRAM programming currents from the power supplies of such devices. That is, if the power supply of the PRAM memory device generates low voltage power supply signal (e.g., about 1.8 V), the write current may be insufficient as the result of one or several excessive voltage drops in the write circuit path.
Moreover, another problem can arise when the reset or set operation is performed in a multi-bit cell format, e.g., a×16-bit format. The accumulative current that is drawn into the memory cells can cause fluctuations in the voltage level of the power supply each time a writing operation is performed.